Firsynth: A CAD tool for high-level FIR filter synthesis

Author

Alpago, Octavio H. ; Zacchigna, Federico G. ; Lutenberg, A.

Author_Institution

Fac. de Ing., Univ. de Buenos Aires, Buenos Aires, Argentina

fYear

2014

fDate

13-15 Aug. 2014

Firstpage

1

Lastpage

6

Abstract

A software tool for high-level synthesis of Finite Impulse Response (FIR) filters is presented. The tool is based on Canonic Signed Digit (CSD) coding for filter coefficients and Nonrecursive Signed Common Subexpression Elimination algorithm (NR-SCSE) for logic operators (adders and subtractors) mini-mization. By means of this tool a fully-synthesizable HDL code can be generated which is suitable for Field Programmable Gates Arrays (FPGA) as well as for Application Specific Integrated Circuits (ASIC). In this paper all the algorithms implemented are described. Logic operators (LOs) are based on ripple carry structures (RCS) in order to save area and simplify routing. The source code was developed in C programming language and can be used under GNU General Public License (GNU-GPL).

Keywords

C language; FIR filters; application specific integrated circuits; field programmable gate arrays; logic CAD; software tools; ASIC; C programming language; CAD tool; CSD coding; FPGA; Firsynth; GNU general public license; GNU-GPL; NR-SCSE; RCS; application specific integrated circuits; canonic signed digit; field programmable gates arrays; finite impulse response filters; high-level FIR filter synthesis; logic operators; nonrecursive signed common subexpression elimination algorithm; ripple carry structures; software tool; Adders; Computer aided software engineering; Conferences; Embedded systems; Finite impulse response filters; Pipelines; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Embedded Systems (SASE/CASE), 2014 Fifth Argentine Symposium and Conference on

Conference_Location

Buenos Aires

Print_ISBN

978-987-45523-0-3

Type

conf

DOI

10.1109/SASE-CASE.2014.6914460

Filename

6914460