EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-off

Author

Talebi, Samaneh ; Abolghasemi, Niloofar ; Jahanian, Ali

Author_Institution

Dept. of Electr., Comput. & Biomed. Eng., Islamic Azad Univ., Qazvin, Iran

fYear

2012

fDate

5-8 Sept. 2012

Firstpage

415

Lastpage

418

Abstract

Architectural advancement in hardware implementation of Java increases the performance. Java processors reduce the overhead of execution time and memory accesses of traditional implementation of JVM in embedded systems. To improve the performance of Java processors and decrease the execution time, we decided to customize a processor is called JOP. We design a Reconfigurable Functional Unit (RFU) which is integrated to JOP´s core for executing the Custom Instructions (CIs) that are generated offline. In this article the efficiency of an extensible Java processor is analyzed with the number of clock cycles in several signal processing application benchmarks. Using this architecture, performance is improved by 31.8% in average compared to basic JOP.

Keywords

Java; clocks; embedded systems; performance evaluation; reconfigurable architectures; signal processing; EJOP; JVM; RFU; architectural advancement; clock cycles; custom instructions; embedded systems; execution time; extensible Java processor; flexibility trade-off; hardware implementation; memory accesses; reconfigurable functional unit; signal processing application benchmarks; Benchmark testing; Clocks; Computer architecture; Educational institutions; Hardware; Java; Pipelines; Custom instruction; Extensible processor; Java processor;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital System Design (DSD), 2012 15th Euromicro Conference on

Conference_Location

Izmir

Print_ISBN

978-1-4673-2498-4

Type

conf

DOI

10.1109/DSD.2012.47

Filename

6386919