A New Technique for Input Protection Testing

Input protection circuits are typically evaluated by resistively discharging a capacitor into the tested device with one or more of its pins grounded. These techniques usually result in junction damage in or near the irnput protection circuit, rather than in gate oxide ruptures as is seen in most electrostatic damage field failures. To eliminate this inconsistency, a new testing technique has been developed. Electro-static failures are modeled as occurring while the affected device is isolated from ground and forced to change potential at an externally determined rate. The nlew technique provides two quantitative parameters, namely the maximum voltage and the rise time of the applied pulse, which yield the voltage slew rate and the power dissipated into the device. By adjusting these paramieters to obtain a predeterrnined failure rate, an accurate comparison of the input protection networks on different devices may be obtained. In addition to reproducing the field failure mechanism, experimiiental data indicates that this technique has sufficient sensitivity to detect slight design variations in almiiost identical input protection circuits.