Title :
A new floorplan simultaneously placing blocks over two logic layers for sea-of-gate gate arrays
Author :
Seki, Mitsuho ; Kobayashi, Shun´ichi ; Takubo, Munehiro ; Kurosawa, Kazuyoshi
Author_Institution :
Hitachi Ltd., Ibaraki, Japan
Abstract :
A new floorplan simultaneously placing blocks defined over two layers is proposed. The objective function considers the interblock wiring length and the area of blocks over two layers. A method for automatic determination of the coefficient between the above two terms is proposed. Experimental results show that the average wiring length inside blocks and the execution time of the proposed floorplan are better than those of a flat-layout and a layer-by-layer floorplan
Keywords :
circuit layout CAD; integrated circuit layout; logic CAD; logic arrays; wiring; execution time; floorplan; interblock wiring length; logic layers; objective function; sea-of-gate gate arrays; Bismuth; Delay; Large-scale systems; Logic arrays; Nonhomogeneous media; Routing; Shape; Simulated annealing; Timing; Wiring;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394084
