Title :
A new schematic-driven floorplanning algorithm for analog cell layout
Author :
Gohar, Nasir-Ud-Din ; Cheung, Peter Y K
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
Abstract :
A new schematic-driven floorplanning algorithm is described. This algorithm improves on initial constructive placement iteratively not only by selecting the best orientation for the module cells, but also by optimizing the floorplan topology through local transformations applied to the polar graph representation of the floorplan. The transformations are easy to implement, efficient to perform and produce compact layout
Keywords :
analogue integrated circuits; cellular arrays; circuit layout CAD; graph theory; iterative methods; network topology; analog cell layout; compact layout; floorplan topology; iterative methods; local transformations; module cells; polar graph representation; schematic-driven floorplanning algorithm; Circuit simulation; Circuit topology; Clustering algorithms; Computational modeling; Digital circuits; Educational institutions; Iterative algorithms; Shape; Simulated annealing; Stochastic processes;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394087
