ROM-based synthesis of fault-tolerant controllers

Author

Wendling, X. ; Rochet, R. ; Leveugle, R.

Author_Institution

CSI, Inst. Nat. Polytech. de Grenoble, France

fYear

1996

fDate

6-8 Nov 1996

Firstpage

304

Lastpage

308

Abstract

Fault tolerance has become a major concern in the design of VLSI systems. It is especially needed in finite state machines (FSMs) where a failure can have huge consequences on the whole circuit behavior. Several methods have been proposed in the last few years to implement such features in FSMs synthesized on standard cells. At the same time, considering circuit cost, performances and design efficiency, it has been shown that large controllers should rather be synthesized on a particular ROM-based architecture. The work presented here has consisted in studying, implementing and evaluating fault tolerance methods in FSMs in a ROM-based synthesis flow

Keywords

VLSI; cellular arrays; circuit CAD; finite state machines; integrated circuit design; logic CAD; read-only storage; sequential circuits; IC design; ROM-based synthesis; VLSI systems; circuit behavior; design efficiency; fault-tolerant controllers; finite state machines; standard cells; synthesis flow; Automata; Automatic control; Circuit synthesis; Computer architecture; Control system synthesis; Costs; Fault tolerance; Integrated circuit synthesis; Read only memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on

Conference_Location

Boston, MA

ISSN

1550-5774

Print_ISBN

0-8186-7545-4

Type

conf

DOI

10.1109/DFTVS.1996.572037

Filename

572037