ROM-based synthesis of fault-tolerant controllers

Fault tolerance has become a major concern in the design of VLSI systems. It is especially needed in finite state machines (FSMs) where a failure can have huge consequences on the whole circuit behavior. Several methods have been proposed in the last few years to implement such features in FSMs synthesized on standard cells. At the same time, considering circuit cost, performances and design efficiency, it has been shown that large controllers should rather be synthesized on a particular ROM-based architecture. The work presented here has consisted in studying, implementing and evaluating fault tolerance methods in FSMs in a ROM-based synthesis flow