An architecture-driven approach for the fitting problem in an application-specific EPLD

Author

Chrzanowska-Jeske, M. ; Goller, S. ; Schafer, I.

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

fYear

1993

fDate

3-6 May 1993

Firstpage

1782

Abstract

An architecture-driven fitting algorithm for an application-specific erasable programmable logic device (EPLD) is described. The specific architecture-dependent constraints imposed on the connectivity of the chip are used to develop a hierarchical partitioning structure of the algorithm. This approach limits very effectively the solution search-space in the early stage of the search process. The program which implements the proposed algorithm has been tested, and the experimental results are very promising. The approach which is based on partitioning can be also applied to other field programmable gate array (FPGA) architectures

Keywords

application specific integrated circuits; field programmable gate arrays; logic CAD; logic arrays; logic partitioning; programmable logic devices; application-specific EPLD; architecture-dependent constraints; architecture-driven approach; connectivity; erasable programmable logic device; field programmable gate array; fitting problem; hierarchical partitioning structure; solution search-space; Control systems; Costs; Field programmable gate arrays; Hardware; Macrocell networks; Partitioning algorithms; Programmable logic arrays; Programmable logic devices; Routing; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394090

Filename

394090