Yield optimization of analog MOS integrated circuits including transistor mismatch

Author

Su, Hua ; Michael, Christopher ; Ismail, Mohammed

Author_Institution

Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA

fYear

1993

fDate

3-6 May 1993

Firstpage

1801

Abstract

With the aid of the SMOS (statistical MOS) model, it is presently possible to simulate random device mismatch effects on the circuit performance. Two different optimization algorithms, which, together with the SMOS model, can create an efficient CAD environment for integrated circuit designers are presented. The goal of these optimizations is for the user to determine the optimal circuit modifications in order to achieve a user specified parametric yield, as well as the nominal circuit specifications. The optimization algorithms use the steepest descent method and the experiment design method with response surface methodology (RSM). Area optimization of a Miller compensated operational amplifier is used as an example

Keywords

MOS analogue integrated circuits; circuit CAD; circuit optimisation; integrated circuit design; integrated circuit yield; operational amplifiers; CAD environment; Miller compensated operational amplifier; SMOS; analog MOS integrated circuits; area optimisation; circuit performance; integrated circuit designers; optimal circuit modifications; random device mismatch effects; response surface methodology; statistical MOS; steepest descent method; transistor mismatch; user specified parametric yield; Algorithm design and analysis; Circuit optimization; Circuit simulation; Design automation; Design methodology; Design optimization; Integrated circuit modeling; Integrated circuit yield; MOS integrated circuits; Response surface methodology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394095

Filename

394095