DocumentCode
261114
Title
VHDL implementation of IEEE 754 floating point unit
Author
Sasidharan, Anjana ; Nagarajan, P.
Author_Institution
AP/ECE, Vivekanandha Coll. of Eng. for Women, Namakkal, India
fYear
2014
fDate
27-28 Feb. 2014
Firstpage
1
Lastpage
5
Abstract
IEEE-754 specifies interchange and arithmetic formats and methods for binary and decimal floating-point arithmetic in computer programming world. The implementation of a floating-point systemusing this standard can be done fully in software, or in hardware, or in any combination of software and hardware. This project propose VHDL implementation of IEEE-754 Floating point unit. In proposed work the pack, unpack and rounding mode was implemented using the VHDL language and simulation was verified.
Keywords
IEEE standards; floating point arithmetic; hardware description languages; programming; IEEE 754 floating point unit; VHDL implementation; computer programming; floating-point arithmetic; Computers; Digital arithmetic; Educational institutions; Encoding; Hardware; Software; Standards; Floating point unit; IEEE754; pack; rounding; unpack;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Communication and Embedded Systems (ICICES), 2014 International Conference on
Conference_Location
Chennai
Print_ISBN
978-1-4799-3835-3
Type
conf
DOI
10.1109/ICICES.2014.7033999
Filename
7033999
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