DocumentCode
2611150
Title
Implementing fault injection and tolerance mechanisms in multiprocessor systems
Author
Auder, D. ; Gagnon, N. ; Savaria, Y.
Author_Institution
Univ. de Quebec, Chicoutimi, Que., Canada
fYear
1996
fDate
6-8 Nov 1996
Firstpage
310
Lastpage
317
Abstract
The size and complexity of today´s multiprocessor systems require the development of new techniques to measure their dependability. An effective technique allowing one to inject faults in message passing multiprocessor systems is presented. Interrupt messages are used to trigger fault injection routines in the targeted processors. Any fault that can be emulated by a modification of the memory content of processors can be injected. That includes faults that could occur within the processors, memories and even in the communication network. The proposed technique allows one to control the time and location of faults as well as other characteristics. It has been used in a prototype multiprocessor system running real applications in order to compare the efficiency of various error detection and correction mechanisms
Keywords
error correction; error detection; fault tolerant computing; message passing; multiprocessing systems; multiprocessor interconnection networks; communication network; dependability; error correction mechanisms; error detection mechanisms; fault injection; fault tolerance mechanisms; interrupt messages; memory content; message passing multiprocessor systems; Application software; Communication networks; Communication system control; Computer errors; Error correction; Hardware; Message passing; Multiprocessing systems; Prototypes; Size measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on
Conference_Location
Boston, MA
ISSN
1550-5774
Print_ISBN
0-8186-7545-4
Type
conf
DOI
10.1109/DFTVS.1996.572038
Filename
572038
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