Title :
On the comparison between architectures for the implementation of distributed arithmetic
Author :
Wolter, S. ; Schubert, A. ; Matz, H. ; Laur, R.
Author_Institution :
Dept. of Electr. Eng., Inst. of Microelectron., Bremen Univ., Germany
Abstract :
Distributed arithmetic (DA) is used as a method for efficient implementation of inner product computation, where the coefficients of one vector are fixed. Different structures for the implementation of DA are compared. The area-time tradeoff study includes processors based on 1) vectors with N = 4, 8, 16 or 32 variables; 2) four different adder circuits with and without pipelining; and 3) two memory saving techniques. The architectures are implemented in a double metal 1.2-μm CMOS technology within a standard cell environment, and are verified by simulations. This allows comparison by means of real values for chip area and computation time
Keywords :
CMOS digital integrated circuits; adders; cellular arrays; digital arithmetic; parallel architectures; pipeline arithmetic; 1.2 micron; CMOS technology; adder circuits; area-time tradeoff; chip area; computation time; distributed arithmetic; inner product computation; memory saving techniques; pipelining; standard cell environment; Adders; Arithmetic; CMOS technology; Circuit simulation; Computational modeling; Computer architecture; Distributed computing; Pipeline processing;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394102
