Via Resistance as a Technique to Control the Electromigration of Non-Overlap Via Holes

The via hole in non-overlap vias is larger than the width of the underlaying metal stripe. The upper metal thins down along the slope of the via hole. The extent of thinning depends upon the angle of the via. The reliability of the via can be assured by the control of the slope of the RIE or wet etched via, but this needs SEM analysis which is not possible on a manufacturing line. A series of life test experiments by the step stress method showed that via chains with high resistance resulted in early fails due to electromigration at the thinned down portion of via, and via chains with normal resistance showed good reliability. The results showed that via reliability can be maintained by controlling the via chain resistance below specified limit during the processing of the semiconductor products.