KaGen-A generator of static CMOS-cell layout from circuit schematics

KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a transfer gate). The system operates in three stages. The circuit is positioned into subcircuits. For each subcircuit, a set of layout-candidates for an optimal cell is generated. In the last step, the cells are placed. During placement, the best fitting cells are chosen from the set of layout-candidates