A Platinuim Silicide Failure Mechanism Involving an Oxygen-Rich Layer

This paper describes a new transistor failure mode on logic devices using PtSi contact metallurgy. Electrically the problem manifested itself by an increase in V(BES). By the use of metallography, microprobe, scanning electron microscopy (SEM) and energy dispersive analysis (EDA), we determined that the high V(BES) was due to the loss of adhesion between the PtSi layer and Si. Auger sputter profiling revealed the presence of an oxygen-rich layer at the PtSi-Si interface only on emitter contacts. Metallographic analysis showed that a buffered HF (BHF) step had electrochemically etched exposed n+ Si at the periphery of the emitter contacts. When the etching had reached the PtSi/Si interface, it gave the buffered HF access to attack the oxygen-rich layer, causing both partial delamination of the PtSi and the high V(BES). During Pt deposition the oxide layer had formed by residual O2 and H2O present in the evaporator. Several changes in the deposition process eliminated the oxygen-rich layer and, hence, the failure mechanism: the installation of a Meissner trap in the evaporator was effective in reducing the water peak during Pt deposition; increased evaporation rate minimized oxygen entrapment; lowering substrate temperature reduced the PtSi reaction rate so that the usual diffusion mechanisms could accumulate any oxide formed during deposition to the Pt2Si/Pt interface rather than the PtSi/Si interface. The oxide at the Pt2Si/Pt interface is removed later by a BHF step that follows aqua regia removal of unreacted Pt.