Low latency architectures for wave digital filters

Wave digital filters constructed of networks of two port adaptors are candidates for VLSI implementation. Pipelining, and hence high data throughput, requires a low latency, high throughput, hardware structure for the two-port adaptor. This design problem is addressed in two main approaches, i.e., with systolic array techniques based on lsb first pipelining that exploit the low coefficient wordlength properties of wave digital filters, and with msb first pipelining based on signed digit number systems. These methods are extended, compared and contrasted; a new hardware scheme is presented; and it is indicated which arrangements are best suited for particular filtering applications