Etchback Method for SEM Investigation of Metal Step Coverage of IC Devices

Coverage by interconnect metal over various heights of the geometrical structure of IC´s can be critical to device performance. Thin metal at steps can become a site for potential failure by a variety of mechanisms.1 SEM examination of devices may routinely be used to verify good step coverage,2 provided faithful samples can be prepared. A chemical etch formulation of phosphoric and acetic acids has been developed to overcome the problems of cross-sectioning. Controlled, reproducible etch rates for aluminum and silicon aluminum interconnect material have been obtained. Exposing a device to the etch for an exact length of time, with subsequent SEM analysis at critical step coverage points, easily reveals if sufficient metal was originally present at the location as required by process specification, e.g. to meet current density requirements. A further feature of the etchback method is its applicability to localized voided regions in metal. Voids may occur at critical step coverage sites, making true metal thickness uncertain and not readily measurable by SEM. A series of careful etching and cross-sectioning experiments, followed by SEM analysis, was carried out to determine etching action within voids. Downward etch rate in the bottom of voids was found to be equal to downward etch rate at the open planar surface of smooth metal. Lateral etch rate within voids was 75% of the downward etch rate. Reproducible performance of the etchback method enables convenient and quick sample preparation for SEM analysis of metal step coverages.