A single chip Lempel-Ziv data compressor

Author

Wei, Belle W Y ; Tarver, R. ; Kim, Jong-Seop ; Ng, Kevin

Author_Institution

Dept. of Electr. Eng., San Jose State Univ., CA, USA

fYear

1993

fDate

3-6 May 1993

Firstpage

1953

Abstract

A single-chip implementation of the Lempel-Ziv adaptive data compression algorithm in 1.2-μm CMOS technology is described. The chip uses 2K-byte on-chip content addressable memory (CAM)/SRAM for storing the most recent input characters to which the incoming string is compared against and referenced. It performs compression or decompression on byte-oriented input data at a data rate of one byte per clock cycle, except when one out of every 33 cycles is used to update the string dictionary

Keywords

CMOS digital integrated circuits; adaptive signal processing; data compression; digital signal processing chips; 1.2 micron; 2 KB; CMOS technology; Lempel-Ziv data compressor; SRAM; adaptive data compression algorithm; byte-oriented input data; decompression; input characters; on-chip content addressable memory; single-chip implementation; string dictionary; CADCAM; CMOS technology; Circuits; Clocks; Computer aided manufacturing; Data compression; Decoding; Dictionaries; Educational institutions; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394133

Filename

394133

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2611772