An efficient architecture for the adaptive filter using delayed LMS algorithm

An efficient architecture for the delayed least mean square adaptive filter based on optimized balanced pipeline and novel partial product generator with two simple components named as decoder and and/or cell is presented in this paper. Finally the bit level pruning technique and fixed point implementation is applied for the proposed structure. The proposed design can be implemented by using various filter lengths. From synthesis results, the less no of slices can be achieved by using Xilinx ISE tool and also less area and power can be achieved by using synopsys tool.