Soft Error Analysis on Communication Channels in On-Chip Communication Networks

Increase in the number of transistors has resulted in more vulnerability of digital systems to soft-errors. For a long time, designers have used the worst case scenarios in their designs to alleviate such disturbances, but due to the overall increase in cost in relation with system performance, manufacturing based on worst case scenarios for transient faults is no longer a viable option. Meanwhile, demand for higher performance systems, multi-core processors, and Networks on Chip (NoC) communication structures are affecting design methodologies, and must be considered while dealing with soft errors. Demand for more flexible and high performance systems have made such communication infrastructures so complex that a perfect error free communication is hard to come by. This paper proposes a method to evaluate the reliability of communication infrastructures in a Multi-Processor System on Chip (MPSoC). In this method, we evaluate vulnerability of communication systems based on data flow vulnerability in the network. The experimental results show estimated values for silence data corruption (SDC) of MPSoC´s communication infrastructures under various routing algorithms and traffic loads.