An implementation of 1-bit low power full adder based on multiplexer and pass transistor logic

A novel implementation of 1 bit full adder based on multiplexer cell is being proposed. This paper presents the design of low power full adder based on XOR pass transistor logic and transmission gate for carry. To reduce the transition activity and charge recycling capability we have not connected power supply rail directly instead of that inputs are given directly and this result in great amount of reduction in power consumption. Power is decreased to a substantial amount while transistor count has gone up to 14T rather 12T. Exhaustive and intensive Tanner SPICE simulation is done and it shows that there is saving of power supply by the factor of 30% as compare to 10T and 26% reduction in power as compare to conventional 28-T CMOS adder[1]-[2].