FPGA based low complexity multipurpose reconfigurable image processor

Digital image processing is mainly focused on ever expanding and dynamic area with applications reaching out into our day today life such as medicine, security purpose, space exploration, surveillance, identification & authentication, automatic industry inspection etc. Applications such as these involve different operations like image enhancement, object detection and Noise removing. Implementing the image processing applications on a computer can be easier one, but not efficient due to additional constraints on memory and other peripheral devices. However, most general purpose hardware is not suited for strong real-time constraints. This paper gives the implementation of median filter image processing on FPGA. The processor´s architecture is combining with a reconfigurable binary processing module, input and output image controller units, and peripheral circuits. Reconfigurable binary processing module will perform median filter operations, for a 180×180 image. The periphery circuits control the whole image processing and dynamic reconfiguration process. The processor is implemented on an EP2C35 field-programmable gate array. The simulation and experimental results demonstrate that the processor is suitable for real-time binary image processing applications.