On-Package Scalability of RF and Inductive Memory Controllers

Orthogonally to the latency aspect, in the multicore era, the memory wall problem further characterizes by concurrent memory accesses which demand more bandwidth, other than power. Multiple memory controllers (MCs) can direct address bandwidth, however MCs scalability is limited by the number and area of I/O pads/pins allocated to them, other than power. In this paper, we propose a design and perform the modeling of multiple Radio-Frequency (RF) and inductive MC (indMC) solutions to address the I/O pin problem restrictions while exploring the architectural benefit of package area to fit ranks connected to these MCs. In this investigation, considering traditional I/O-constrained electrical-MC solution as a baseline, we observe that these on-package multiple MC solutions improve performance by a factor of up to 3.55x for a 16-OOO-core system, with different core:MC ratios and memory intensive applications. Since bandwidth and latency are related, average latency is reduced of up to 47%.