DocumentCode :
2612025
Title :
A parallel SONET scrambler/descrambler architecture
Author :
Seetharam, Srini W. ; Minden, Gary J. ; Evans, Joseph B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Kansas Univ., Lawrence, KS, USA
fYear :
1993
fDate :
3-6 May 1993
Firstpage :
2011
Abstract :
Scrambling of the bits in a synchronous optical network (SONET) frame is needed to keep the frequency content of the transmitted signals near the actual line rate, while descrambling is required on the receive end of a SONET transceiver in order to retrieve the actual bits that comprised the SONET frame. For any SONET line rate above the OC-1 (51.840 Mb/s), this operation is difficult using the conventional bit serial architecture. It is demonstrated how scrambling and descrambling can be performed on an OC-12 SONET frame (622 Mb/s) using word level parallelism. This architecture enables the SONET scramble/descramble operations to be performed on field programmable gate arrays
Keywords :
SONET; field programmable gate arrays; optical fibre communication; parallel architectures; programmable logic arrays; transceivers; 622 Mbit/s; OC-12 SONET frame; field programmable gate arrays; frequency content; line rate; scrambler/descrambler architecture; synchronous optical network; transceiver; word level parallelism; Asynchronous transfer mode; B-ISDN; Computer architecture; Computer networks; Frequency; Laboratories; Payloads; SONET; Telecommunication computing; Telecommunication standards;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
Type :
conf
DOI :
10.1109/ISCAS.1993.394148
Filename :
394148
Link To Document :
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