Design issues for SiGe heterojunction FETs

Important SiGe HFET design issues are discussed and confirmed after the fabrication of subsurface graded SiGe-channel modulation-doped p-MOSFETs. By grading the SiGe channel profile, the location of the carrier flow can be controlled and the transconductance optimized. The use of an n⁺-polysilicon gate design minimizes the parasitic Si surface conduction and maximizes the amount of high mobility holes confined to the channel. With modulation doping, the mobility is enhanced and freeze-out at low temperature is eliminated. Locating the dopant atoms below the channel minimizes process sensitivity and improves the transconductance. Application of these design concepts resulted in functional submicron SiGe p-MOSFETs with low-field hole mobilities of 220 cm²/V-s at 300 K and 980 cm²/V-s at 82 K. These results illustrate the importance of an optimized device design; they also demonstrate the feasibility of graded SiGe-channel modulation-doped p-MOSFETs and their leverage over conventional Si p-MOSFETs