Title :
A single chip high data rate QPSK demodulator
Author :
Wagner, D. ; Kwatra, S.C. ; Jamali, M.M.
Author_Institution :
Dept. of Electr. Eng., Toledo Univ., OH, USA
Abstract :
A single chip VLSI design of a digital quadrature-phase-shift-keying (QPSK) demodulator for satellite communication purposes is presented. The digital demodulator uses an optimized phase recovery scheme suitable for single chip implementation. It also uses an efficient timing recovery scheme based on XOR transition detection. The demodulator is suitable for time-division-multiplexing (TDM) applications and can give a speed of 50 Mbps
Keywords :
VLSI; demodulators; integrated circuit design; quadrature phase shift keying; satellite communication; time division multiplexing; timing; 50 Mbit/s; QPSK demodulator; XOR transition detection; optimized phase recovery scheme; quadrature-phase-shift-keying; satellite communication; single chip VLSI design; time-division-multiplexing; timing recovery scheme; Baseband; Costs; Demodulation; Fabrication; Low pass filters; Quadrature phase shift keying; Satellite communication; Time division multiplexing; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394153
