A parallel force direct based VLSI standard cell placement algorithm

Author

Horvath, E.I.

Author_Institution

Dept. of Comput. Sci. & Eng., Florida Atlantic Univ., Boca Raton, FL, USA

fYear

1993

fDate

3-6 May 1993

Firstpage

2071

Abstract

A new heuristic algorithm is described. It can be used to minimize the weighted wire length in the placement of modules in VLSI chips. A salient feature of PIREN2.0 is that multiple permutations based upon the connectivity between the modules are made simultaneously on all modules in order to minimize the objective function. This allows the algorithm, without major modifications, to be mapped to a processor array structure, the MasPar MP-2.2. Each processor in this massively parallel single instruction, multiple data (SIMD) machine can perform in parallel the computation necessary to place cells in an optimum relative location to one another based upon the connectivity (the number of wires) between cells. A speedup for the benchmark circuits of at least 7.5 is obtained from the parallel version without degrading the quality of the layout solution

Keywords

VLSI; cellular arrays; circuit layout CAD; logic CAD; logic partitioning; parallel algorithms; MasPar MP-2.2; PIREN2.0; SIMD machine; VLSI; benchmark circuits; connectivity; heuristic algorithm; modules; multiple permutations; objective function; optimum relative location; processor array structure; standard cell placement algorithm; weighted wire length; Circuits; Concurrent computing; Degradation; Parallel processing; Partitioning algorithms; Process design; Routing; Simulated annealing; Very large scale integration; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394156

Filename

394156