A flexible ASIP decoder for combined binary and non-binary LDPC codes

This paper describes the implementation of a flexible combined binary and non-binary LDPC decoder. The ASIP architecture can be configured allowing re-use between both modes. Key in the architecture is parallelization, which is exploited in the SIMD engine. Binary LDPC codes intrinsically enables parallelization through layered decoding while in the non-binary case different trade-offs can be made. The implementation choice was made base on minimal memory requirement and computational effort. For a combination of supporting binary LDPC present within WLAN and WiMAX standard with non-binary GF(8) LDPC codes, a total area of 5.4 sqmm in commercial 65nm technology would be required. This size can be reduced towards 3.4 sqmm if only half of the non-binary decoding throughput is required.