Optimization of dynamic power and speed by trade off filter performance

FIR digital filters are used in Digital Signal Processing (DSP) by the virtue of its, linear phase, fewer finite precision error, stability and efficient implementation. This paper presents an architectural approach to the design of High speed reconfigurable finite impulse response (FIR) filter. In this paper new reconfigurable low power FIR filter architecture using Multiplier Control Decision Window(MCSD) is proposed. The approach is well suited when the filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and filter performance can be made using the proposed architecture. Thus the proposed architecture offers 20% power efficiency and 40% delay reduction compared to the best existing reconfigurable FIR filter. This has been implemented and tested on Spartan-3 xc3s200-5pq208 field-programmable gate array (FPGA).