DocumentCode
2612231
Title
Reducing the physical design cycle by means of topological placement with hard timing restraints
Author
Freier, Bernd E.
Author_Institution
GMD-SET, St. Augustin, Germany
fYear
1993
fDate
3-6 May 1993
Firstpage
2063
Abstract
A new concept for topological module placement satisfying hard timing restraints based on segmenting the layout surface into topological rings is introduced. By using this method it is possible to shorten the layout-extraction-relayout cycle significantly, because the resulting placement satisfies user defined signal run-times. The new method can be applied to hierarchical layout systems, and is flexible in terms of design styles and module specifications
Keywords
VLSI; circuit layout CAD; integrated circuit layout; network topology; timing; design styles; hard timing restraints; hierarchical layout systems; layout surface; layout-extraction-relayout cycle; module placement; module specifications; physical design cycle; topological placement; topological rings; user defined signal run-times; Algorithm design and analysis; Circuits; Clocks; Delay effects; Pins; Relays; Sorting; Surface topography; Time to market; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394162
Filename
394162
Link To Document