Automatic generation of transistor stacks for CMOS analog layout

Author

Liberali, Valentino ; Malavasi, Enrico ; Pandini, Davide

Author_Institution

Dipartimento di Elettronica, Pavia Univ., Italy

fYear

1993

fDate

3-6 May 1993

Firstpage

2098

Abstract

A layout-driven approach to the design of analog cells is described. MOS transistor stacks can be generated by splitting transistors with large W/L into modules, and then compacting them by means of a chaining algorithm. The choice of the optimum stack abutment relies on sensitivity analysis, constraint generation and minimization of a cost function accounting for parasitic control and area optimization

Keywords

CMOS analogue integrated circuits; cellular arrays; circuit layout CAD; integrated circuit layout; network topology; sensitivity analysis; CMOS analog layout; MOS transistor; analog cells; area optimization; chaining algorithm; constraint generation; cost function; layout-driven approach; optimum stack abutment; parasitic control; sensitivity analysis; transistor stacks; Analog circuits; Automatic control; Circuit simulation; Constraint optimization; Cost function; Humans; MOSFETs; Minimization; Routing; Sensitivity analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394170

Filename

394170

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2612336