Title :
Jitter due to signal history in digital logic circuits and its control strategies
Author :
Lin, Pemg-Shyong ; Zukowski, Charles A.
Author_Institution :
Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Abstract :
The circuit throughput of a logic channel in some high-speed applications is limited by the quality of the transition edge. One important limitation to this quality comes from jitter, especially that arising from signal history. The cause of this type of jitter is discussed, and its accumulation is explored. Some jitter reduction techniques are analyzed
Keywords :
circuit noise; clocks; jitter; logic circuits; accumulation; circuit throughput; control strategies; digital logic circuits; high-speed applications; jitter reduction; logic channel; signal history; transition edge; Clocks; Data communication; Driver circuits; History; Logic circuits; Phase locked loops; Pipeline processing; Propagation delay; Throughput; Timing jitter;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394174
