Speed optimization of edge-triggered nine-transistor D-flip-flops for gigahertz single-phase clocks

An analysis is performed on one of the recently published D-flip-flops in order to show the conflicting nature of the requirements for sizing each transistor in a digital circuit. The decision process is complex because the electrical parameters (such as gate capacitance and drain current) of an MOS transistor are functions of terminal waveforms which change rapidly with time, and are different from one state-transition to another. A better understanding of the operation of such digital circuits during each state-transition helps the human designer and the computer tool to reach a better compromise in a shorter design time. A new D-flip-flop configuration is presented which enables gigahertz clock speeds to be easily achieved for 2-μm and 1.5-μm standard CMOS technologies