Title :
Comparative analysis of LUT design In FPGA
Author :
Firdous, Ayesha ; Rajan, B.
Author_Institution :
ECE Dept., Dr. M.G.R. Educ. & Res. Inst. Univ., Chennai, India
Abstract :
In FPGA, Look Up Tables (LUT) and routing multiplexer are configured using SRAMs. The Look Up Table also a multiplexer that implements a truth table each input combination generates a certain output. The inputs of the Look Up Table is connected to the SRAM cells. There are many ways to design a logic block; one approach is to use multiplexer. This paper represents the simulation of different multiplexer structures for Look Up Table design.
Keywords :
SRAM chips; field programmable gate arrays; logic design; multiplexing equipment; table lookup; FPGA; SRAM; field programmable gate arrays; look up tables; multiplexer; Field programmable gate arrays; Logic gates; Multiplexing; Routing; SRAM cells; Table lookup; Transistors; FPGA; LUT; SRAM; multiplexer;
Conference_Titel :
Information Communication and Embedded Systems (ICICES), 2014 International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4799-3835-3
DOI :
10.1109/ICICES.2014.7034160
