Title :
Architectural descriptions for FPGA circuits
Author_Institution :
Dept. of Comput. Sci., Glasgow Univ., UK
Abstract :
FPGA-based synthesis roofs require information about behaviour and architecture to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices
Keywords :
field programmable gate arrays; hardware description languages; logic arrays; FPGA circuits; FPGA-based synthesis roofs; architectural descriptions; circuit architecture; hardware description language; source level information; Automata; Circuit synthesis; Computer languages; Design methodology; Field programmable gate arrays; Global communication; Hardware design languages; Merging; Optimization methods; Routing;
Conference_Titel :
FPGAs for Custom Computing Machines, 1995. Proceedings. IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-7548-9
DOI :
10.1109/FPGA.1995.477420
