DocumentCode :
261292
Title :
Fault-tolerance of reconfigurable logic in memory using AGT
Author :
Subashini, C. ; Mohanapriya, T. ; Rajaram, Uma
Author_Institution :
Dr. M.G.R. Educ. & Res. Inst. Univ., Chennai, India
fYear :
2014
fDate :
27-28 Feb. 2014
Firstpage :
1
Lastpage :
5
Abstract :
Fault handling is an important metric for many operating environments. The traditional technique for improving reliability of system is by replicating the system component. This paper explains about the Adaptive group testing technique for isolating the faults which is present in the memory of the system. The memory element contains many cell and these cells are grouped into number of blocks. These blocks are tested. The test vectors are produced sly LFSR and this is introduced into the circuit to validate the correct working of the system. This work is incorporated into FPGA to provide an adaptive hardware system with self-isolating properties. This approach increases the performance of the system. This testing is designed using hardware description language called VHDL.
Keywords :
fault tolerant computing; hardware description languages; reliability; storage management; AGT; FPGA; VHDL; adaptive group testing technique; adaptive hardware system; fault handling; fault-tolerance computing; hardware description language; reconfigurable logic; reliability; self-isolating properties; sly LFSR; test vectors; Circuit faults; Computer architecture; Educational institutions; Fault tolerant systems; Field programmable gate arrays; Microprocessors; Testing; AGT; BIST; SRAM;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information Communication and Embedded Systems (ICICES), 2014 International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4799-3835-3
Type :
conf
DOI :
10.1109/ICICES.2014.7034177
Filename :
7034177
Link To Document :
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