Reduction of partial product matrix for high-speed single or multiple constant multiplication

Multiplication by one or several constants is a frequently required arithmetic operation in many DSP functions. A fast and low power implementation for single constant multiplication based on Canonical Signed Digit (CSD) was proposed by Pai et al. to extend it for multiple constant multiplication, two upper bounds for the number of partial product rows were derived. The general upper bound depends only on the bit width of the variable and the specific upper bound depends on both the bit width of the variable and the number of nonzero digits of the CSD encoded constant. Their implications on the logic depth for the carry propagate adder implementation and the depth of the carry save adder tree are analyzed. This paper present an interesting fact that if the constant requires more nonzero digits to be represented than the input bit width, the number of partial product rows can be reduced and leads to a faster and simpler implementation than the direct CSD implementation. The improvements in terms of the maximal possible and average partial product rows are also shown for some constant coefficient FIR filters examples, where the reduction ranges from none to 71% depending on the input bit width. Besides the reduction in the height of the partial product matrix, an example is also presented to show that up to 56% of full and half adders can be shared for multiple constant multiplication.