DocumentCode
2613237
Title
Influence of wiring parasitics on CMOS logic gates
Author
Rodoni, Lucio Carlo ; Ellinger, Frank ; Von Büren, George ; Jäckel, Heinz
Author_Institution
Electron. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland
Volume
3
fYear
2003
fDate
20-23 Sept. 2003
Abstract
This paper investigates the influence of parasitic interconnections on high speed logic gates. A complementary metal oxide semiconductor logic (CMOS) gate, a high speed source coupled logic (SCL) gate and a low power SCL gate are compared. The important impact of the wiring parasitics on the speed performances is pointed out. The results are confirmed with test circuits, fabricated on commercial 0.25 μm CMOS technology.
Keywords
CMOS logic circuits; high-speed integrated circuits; integrated circuit interconnections; integrated circuit testing; logic gates; 0.25 micron; CMOS logic gates; CMOS technology; complementary metal oxide semiconductor logic gate; high speed logic gate; low power source coupled logic gate; parasitic interconnections; wiring parasitics; CMOS logic circuits; CMOS technology; Circuit testing; Circuit topology; Logic gates; MOS devices; MOSFETs; Parasitic capacitance; Pulse inverters; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave and Optoelectronics Conference, 2003. IMOC 2003. Proceedings of the 2003 SBMO/IEEE MTT-S International
Print_ISBN
0-7803-7824-5
Type
conf
DOI
10.1109/IMOC.2003.1271850
Filename
1271850
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