• DocumentCode
    2613396
  • Title

    Reduction of VT Shift Due to Avalanche-Hot-Carrier Injection using Graded Drain Structures in Submicron N-Channel MOSFET

  • Author

    Noyori, M. ; Nakata, Y. ; Odanaka, S. ; Yasui, J.

  • Author_Institution
    Central Research Laboratory, Matsushita Electric Industrial Co., Ltd., 3-15 Yakumo-nakamachi, Moriguchi, Osaka, JAPAN 570
  • fYear
    1984
  • fDate
    30773
  • Firstpage
    205
  • Lastpage
    209
  • Abstract
    In order to evaluate the VT shift due to hot-carriers in submicron n-channel FETs with several kinds of graded junction structures as compared with a conventional structures, long term stress tests were conducted. As a result, it was found that the VT shifts observed in these devices were caused not by channel-hot-electron but by an avalanche-hot-carrier, which is probably a hot hole, and that the VT shift can be suppressed pronouncedly by the graded drain structures. This paper describes VT shift characteristics due to avalanche-hot-carriers compared with those due to channel-hot-carriers as well as the analysis of VT shift reduction mechanism in the graded drain structured devices.
  • Keywords
    Annealing; CMOS technology; Double-gate FETs; Etching; Ion implantation; Laboratories; MOSFET circuits; Plasma temperature; Stress; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 1984. 22nd Annual
  • Conference_Location
    Las Vegas, NV, USA
  • ISSN
    0735-0791
  • Type

    conf

  • DOI
    10.1109/IRPS.1984.362046
  • Filename
    4208570