ASIC design of UHF RFID reader digital baseband

This paper presents the ASIC design and implementation of digital baseband system for UHF RFID reader based on EPC Global C1G2 /ISO 18000-6c protocol. The digital baseband system consists of two parts: transmitter and receiver, which inculing encoding module, decoding module, channel filers, CRC chenk module, control module and a SPI module. It is described in verilog HDL in RTL level, with Design Compiler for synthesizing, PT for static timing analyzing and Astro for physical design. The die is fabricated using IBM 130nm 8-layer-metal RF cmos process successfully, which size is 3 mm × 3mm, the power consumption is around 6.7mW. It can be applied in the research of single-chip UHF RFID reader.