The integrated implementation of Whirlpool and AES on FPGA

Author

He, Jianhua ; Chen, Hu ; Huang, Huaqiang

Author_Institution

Comput. Sci. & Eng., South China Univ. of Technol., Guangzhou, China

fYear

2010

fDate

22-24 Sept. 2010

Firstpage

251

Lastpage

254

Abstract

Advanced Encryption Standard (AES) is one of the latest symmetric key cryptosystem standard, which is proposed to replace DES. Whirlpool is a famous hash encryption algorithm that processes the building blocks in a similar way. Although some slight differences are presented, implementing an integrated design of AES and Whirlpool on the FPGA can reduce the overall area. Further more, it provides a scaleable implementation of trust platform module (TPM) which is the trust root of trusted computing. In this paper, an optimized design of the register array is addressed, and it reduces about 65% of the area and makes this integrated design be implemented in low-end FPGAs.

Keywords

cryptography; field programmable gate arrays; Whirlpool; advanced encryption standard; hash encryption algorithm; low-end FPGA; register array; symmetric key cryptosystem standard; trust platform module; trust root; trusted computing; Algorithm design and analysis; Arrays; Field programmable gate arrays; Random access memory; Shift registers; Throughput; AES; FPGA; Trust Compute Module; Whirlpool;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in

Conference_Location

Shanghai

Print_ISBN

978-1-4244-6735-8

Electronic_ISBN

978-1-4244-6736-5

Type

conf

DOI

10.1109/PRIMEASIA.2010.5604915

Filename

5604915