A 62MHz~316MHz Phase-Locked Loop Based on Ring Oscillator for ADC Clock Generator in 0.18m CMOS

This paper presents a design and implementation of a low noise phase-locked loop (PLL) based on ring oscillator to provide timing clocks for the analog-to-digital converter (ADC). The ring oscillator consists of four current control delay cells with current-steering amplifier (CSA) circuit. These fully switching differential delay cells are employed to reduce the phase noise of the ring oscillator. The ring oscillator exhibits a wide tuning range from 62 MHz to 316 MHz. For the low noise structure, the total phase noise of the PLL is about-113.5 dBc/Hz at 1 MHz offset frequency. The PLL is designed in a 0.18 μm CMOS process and takes up a layout area of only 280 × 300 μm2, while consuming 0.9 mA current from a 1.8 V supply.