Buffer design based on flow control in RapidIO

Author

Zhao, Xiongbo ; Jia, Song ; Wang, Yuan ; Wu, Guirong ; Wu, Fengfeng ; Yang, Kai

Author_Institution

Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China

fYear

2010

fDate

22-24 Sept. 2010

Firstpage

150

Lastpage

153

Abstract

RapidIO is an open standard that provides high-performance interconnect for chip-to-chip, board-to-board, and chassis-to-chassis communications. In this paper, we present an executable RapidIO interconnect in which an improved Buffer structure based on flow control is put forward. It helps to provide a smooth data flow, strong built-in error detection and error recovery mechanisms. It is tested to increase utilization and lower packet latency. And it can be applied to reliable and high speed embedded system communications.

Keywords

buffer storage; embedded systems; multiprocessing systems; multiprocessor interconnection networks; Buffer design; board-to-board communication; chassis-to-chassis communication; chip-to-chip communication; embedded system communication; error detection mechanism; error recovery mechanism; flow control; packet latency; rapidIO interconnect; Embedded system; Integrated circuit interconnections; Performance evaluation; Physical layer; Protocols; Receivers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in

Conference_Location

Shanghai

Print_ISBN

978-1-4244-6735-8

Electronic_ISBN

978-1-4244-6736-5

Type

conf

DOI

10.1109/PRIMEASIA.2010.5604938

Filename

5604938