• DocumentCode
    2614492
  • Title

    A 1.1 GHz 8B/10B encoder and decoder design

  • Author

    Wang, Qi ; Hua, Si-Liang ; Wang, Dong-Hui

  • fYear
    2010
  • fDate
    22-24 Sept. 2010
  • Firstpage
    138
  • Lastpage
    141
  • Abstract
    This paper presents a design of 8B/10B encoder and decoder with a new architecture. The proposed 8B/10B encoder and decoder are implemented based on pipeline and parallel processing. The decoder implements an error-undiffusing function. This 8B/10B encoder and decoder can be used in the high-speed interconnection between chips. After being synthesized using CMOS 90nm process, the proposed encoder and decoder achieves the operating frequency over 1.1GHz and occupies the chip area of 1798μm2 and 1261μm2. They each consume 1.8mW and 1.12mW power.
  • Keywords
    decoding; encoding; parallel processing; pipeline processing; CMOS; decoder design; encoder design; frequency 1.1 GHz; high speed interconnection; parallel processing; pipeline processing; power 1.12 mW; power 1.8 mW; size 90 nm; CMOS integrated circuits; CMOS technology; Data communication; Decoding; Encoding; Pipelines; Transforms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-6735-8
  • Electronic_ISBN
    978-1-4244-6736-5
  • Type

    conf

  • DOI
    10.1109/PRIMEASIA.2010.5604943
  • Filename
    5604943
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2614492