• DocumentCode
    2614624
  • Title

    A digital background nonlinearity calibration algorithm for pipelined ADCs

  • Author

    Fei, Yuan ; Sin, Sai-Weng ; Seng-Pan, U. ; Martins, Rui Paulo

  • Author_Institution
    Analog & Mixed Signal VLSI Lab., Univ. of Macau, Macao, China
  • fYear
    2010
  • fDate
    22-24 Sept. 2010
  • Firstpage
    115
  • Lastpage
    118
  • Abstract
    This paper presents a new digital background calibration algorithm for pipelined analog-to-digital converters (ADCs). Background calibration can extract calibration data without interrupting ADCs normal conversion operation. Digital calibration can relax the design difficulty of analog circuits of ADCs, and gains the improvement of technology scaled down. This algorithm provides a method to effectively estimate the nonlinearity of op amp, and calibrates it in digital domain without any additional analog circuit. Simulation results show that the ENOB can be improved from 6.3b to 10.67b by the proposed algorithm.
  • Keywords
    analogue-digital conversion; calibration; analog circuits; analog-to-digital converters; background calibration; digital background nonlinearity calibration algorithm; pipelined ADC; Algorithm design and analysis; Analog-digital conversion; Calibration; Gain; Mathematical model; Pipelines; Polynomials;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4244-6735-8
  • Electronic_ISBN
    978-1-4244-6736-5
  • Type

    conf

  • DOI
    10.1109/PRIMEASIA.2010.5604949
  • Filename
    5604949