An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio

Major functions of ldquoSoftware Defined Radios( SDRs )rdquo are signal processing functions (SPF) and the basic building blocks for most of these functions are multipliers, adders, delays, square roots, trigonometric functions etc.. The SPFs are computationally intensive and they exhibit spatial or temporal parallelism or both. While the high performance DSP processors are unable to meet the speed requirements of these SDRs, System on chips (SOCs) are also not suitable because of their limited flexibility. Recently, state-of-the-art FPGAs have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions because of the availability of in-built multiply and accumulate (MAC) units within these chips. Hence, FPGAs are becoming possible hardware platforms for implementing SDRs. Apart from that these FPGAs also include partial reconfiguration features that make them suitable for implementing SDRs efficiently as the configuration latency in run time trends to go down. This paper investigates the potential use of FPGAs for implementing efficient ldquoRadio Processorrdquo. The proposed Processor is based on a parallel re-configurable which was implemented on FPGA and exploits the spatial and temporal parallelism of the signal processing functions using a new concept ldquoReconfigurable Single Function Multiple Data (RSFMD)rdquo architecture. The architecture was validated on Xilinx Virtex IV FPGA.