A novel design of dual ladder resistor D/A converter

Author

Huigang, Liu ; Weidong, Geng ; Yanyan, Liu

Author_Institution

Tianjin Key Lab. for Photo-Electron. Thin Film Devices & Technol., Nankai Univ., Tianjin, China

fYear

2010

fDate

22-24 Sept. 2010

Firstpage

65

Lastpage

68

Abstract

This paper presents a novel dual ladder resistor D/A converter architecture. A 10 bits D/A converter is implemented which is based on this architecture. The present architecture provides a novel decoding scheme for dual ladder resistor D/A converter that reduces the size of the decoding logic, reduces the number of switches in coarse resistor stage and fine resistor stage. Experience of the 10 bits D/A converter design was shared. The design achieves INL and DNL of +0.3/-0.4LSB, +0.5/-0.4 LSB. This 10 bits D/A converter was used in reference voltage source chip which was taped out by Chartered 0.35μm CMOS 2P4M Mixed-mode process.

Keywords

CMOS integrated circuits; decoding; digital-analogue conversion; ladder networks; mixed analogue-digital integrated circuits; network synthesis; reference circuits; CMOS 2P4M mixed-mode process; decoding logic; dual ladder resistor D/A converter; reference voltage source chip; size 0.35 mum; word length 10 bit; CMOS integrated circuits; Decoding; Matrix converters; Parasitic capacitance; Resistors; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in

Conference_Location

Shanghai

Print_ISBN

978-1-4244-6735-8

Electronic_ISBN

978-1-4244-6736-5

Type

conf

DOI

10.1109/PRIMEASIA.2010.5604961

Filename

5604961