DocumentCode
2614950
Title
ESD Protection Reliability in 1μM CMOS Technologies
Author
Duvvury, C. ; McPhee, R.A. ; Baglee, D.A. ; Rountree, R.N.
Author_Institution
Semiconductor Advanced Development, Texas Instruments Incorporated, M/S 657 P.O. Box 1443, Houston, Texas 77001. (713) 274-3683
fYear
1986
fDate
1-3 April 1986
Firstpage
199
Lastpage
205
Abstract
The use of graded drains and silicided diffusions are shown to severely degrade Electrostatic Protection circuits when compared to their performance with traditional processing technology. The impact of each of these process options on the protection circuit sizing and the particular failure modes observed are reported here.
Keywords
CMOS technology; Circuits; Conductivity; Degradation; Electrons; Electrostatic discharge; Failure analysis; Isolation technology; Protection; Sheet materials;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 1986. 24th Annual
Conference_Location
Anaheim, CA, USA
ISSN
0735-0791
Type
conf
DOI
10.1109/IRPS.1986.362134
Filename
4208665
Link To Document