• DocumentCode
    2615076
  • Title

    Accurate modeling and fault simulation of Byzantine resistive bridges

  • Author

    Cheung, Hugo ; Gupta, Sandeep K.

  • Author_Institution
    Texas Instrum., Dallas, TX
  • fYear
    2007
  • fDate
    7-10 Oct. 2007
  • Firstpage
    347
  • Lastpage
    353
  • Abstract
    Many recent studies show that a resistive bridging fault may cause intermediate voltages at the bridging fault site. Since the gates in the fanout of the fault site may have distinct and multiple logic threshold voltages, namely VIL and VIH, these gates may interpret the intermediate voltage as logic ´1´, logic ´0´, or logically indeterminate. Such fault behavior is described as the bridging fault Byzantine general problem (T. Nanya et al., Nov. 1989). None of the existing models of bridging faults used by bridging fault simulators accurately captures the indeterminate logic behavior of such bridges. We present a resistive bridging fault model that accurately yet efficiently captures indeterminate logic values. We also describe an efficient PPSFP bridging fault simulator and show that all previous approaches seriously overestimate bridging fault coverage.
  • Keywords
    circuit simulation; fault simulation; logic gates; logic testing; Byzantine resistive bridge fault simulation; logic gates; logic testing; multiple logic threshold voltage; Bridge circuits; Circuit faults; Fabrication; Instruments; Logic gates; Logic testing; RF signals; Switches; Threshold voltage; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2007. ICCD 2007. 25th International Conference on
  • Conference_Location
    Lake Tahoe, CA
  • ISSN
    1063-6404
  • Print_ISBN
    978-1-4244-1257-0
  • Electronic_ISBN
    1063-6404
  • Type

    conf

  • DOI
    10.1109/ICCD.2007.4601923
  • Filename
    4601923