Title :
An energy recovery D flip-flop for low power semi-custom ASIC design
Author :
Lv, Junsheng ; Liu, Hainan ; Ye, Mao ; Zhou, Yumei
Author_Institution :
Inst. of Microelectron., Chinese Acad. of Sci., Beijing, China
Abstract :
A sense amplifier D flip-flop with reset function using energy recovery technique, SAERDR (Sense Amplifier Energy Recovery D Flip-flop with Reset Function), is presented. The proposed flip-flop operates with a single phase sinusoidal clock to recover the energy of the clock pin. Simulation results show that the power consumption of clock pin is saving 72% on average as compared to the same implementation using the square-wave clocking scheme for clock frequencies ranging from 10MHz to 60MHz. We also propose a methodology to design a semi-custom energy recovery ASIC using SAERDR. In the SMIC 0.13μm CMOS process, a numerical controlled oscillator using our methodology is implemented. Test results show the total power saving is up to 34.9% as compared to the implementation using the conventional D flip-flops MSD (Master Salve D Flip-flop) at 60MHz.
Keywords :
CMOS logic circuits; amplifiers; application specific integrated circuits; clock and data recovery circuits; flip-flops; integrated circuit design; logic design; SAERDR; SMIC CMOS process; application specific integrated circuit; clock frequency; clock pin energy recovery; clock pin power consumption; frequency 10 MHz to 60 MHz; low power semicustom energy recovery ASIC design; numerical controlled oscillator; sense amplifier energy recovery D flip-flop with reset function; single phase sinusoidal clock; size 0.13 mum; total power saving; Adders; Application specific integrated circuits; Clocks; Design methodology; Flip-flops; Oscillators; Power demand;
Conference_Titel :
Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-6735-8
Electronic_ISBN :
978-1-4244-6736-5
DOI :
10.1109/PRIMEASIA.2010.5604970
