An energy recovery D flip-flop for low power semi-custom ASIC design

A sense amplifier D flip-flop with reset function using energy recovery technique, SAERDR (Sense Amplifier Energy Recovery D Flip-flop with Reset Function), is presented. The proposed flip-flop operates with a single phase sinusoidal clock to recover the energy of the clock pin. Simulation results show that the power consumption of clock pin is saving 72% on average as compared to the same implementation using the square-wave clocking scheme for clock frequencies ranging from 10MHz to 60MHz. We also propose a methodology to design a semi-custom energy recovery ASIC using SAERDR. In the SMIC 0.13μm CMOS process, a numerical controlled oscillator using our methodology is implemented. Test results show the total power saving is up to 34.9% as compared to the implementation using the conventional D flip-flops MSD (Master Salve D Flip-flop) at 60MHz.