• DocumentCode
    2615323
  • Title

    Power efficient register file update approach for embedded processors

  • Author

    Ayoub, Raid ; Orailoglu, Alex

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Univ. of California at San Diego, La Jolla, CA
  • fYear
    2007
  • fDate
    7-10 Oct. 2007
  • Firstpage
    431
  • Lastpage
    437
  • Abstract
    In this paper we present an approach for a low power register file in the domain of embedded processors. The suggested approach obtains power savings through tackling the unnecessary writes to register files for short live registers. Writes to register files are essentially redundant when an instruction manages to forward its results to all of its dependents through forwarding hardware. As the percentage of registers that exhibit short liveness is shown to be significant, tackling unnecessary writes contributes to delivering appreciable power savings. In this work we show that tackling the unnecessary writes could be attained efficiently through a register based encoding scheme. The suggested encoding scheme exploits application-specific information and renames all or most of the short live registers to a small subset of the registers that are prespecified during the hardware design. The renaming process is performed at the compiler level. Power savings can be obtained through precluding the set of prespecified registers from writing to the register file. We suggest in this paper efficient algorithms for the purpose of renaming, one algorithm to perform the renaming in the cases of no register pressure and another one for the cases of register pressure. In the cases of register pressure, some of the prespecified registers may need to be turned into normal registers, a process that is managed through the use of reprogrammable hardware support. Although the cases of register pressure could impact power savings, the detailed analysis we outline shows that the size of the prespecified registers subset is typically small which makes register pressure an infrequent event. Experimental analysis on numerical and DSP codes indicates appreciable improvements in power savings.
  • Keywords
    file organisation; program compilers; DSP codes; application-specific information; compiler level; embedded processors; infrequent event; normal registers; power efficient register file update approach; power savings; register based encoding scheme; reprogrammable hardware support; short live registers; unnecessary writes; Batteries; Costs; Encoding; Hardware; Heat sinks; Power dissipation; Registers; Temperature; Usability; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2007. ICCD 2007. 25th International Conference on
  • Conference_Location
    Lake Tahoe, CA
  • ISSN
    1063-6404
  • Print_ISBN
    978-1-4244-1257-0
  • Electronic_ISBN
    1063-6404
  • Type

    conf

  • DOI
    10.1109/ICCD.2007.4601935
  • Filename
    4601935